As it is well known in this specific field of application, the urgent request by the world market for semiconductors having high-density non-volatile memories, for example of the Flash EEPROM type, led to the study and application of so-called multilevel memory devices wherein each single memory cell is capable of storing more than one bit. Each bit is associated with a predetermined logic level and level identification is allowed by the use of reference memory cells respectively having multiple threshold voltage levels.
It is quite evident to the skilled in the art that when the number of threshold voltage levels increases, the requirements needed for correctly performing the operations carried out on the cells also increase; i.e., the erasing, programming and reading operations.
In fact, for reliability reasons, the available voltage for allocating the 2n−1 threshold distributions (all but the most programmed one) of a multilevel non-volatile memory having n bits/cell is lower than 4.5-5V. Consequently, both the amplitudes of threshold distributions and the edges between them decrease.
Therefore, in the manufacturing step of multilevel memory devices, it is taken into consideration a series of phenomena being instead totally negligible in traditional two-level memories.
For a better understanding of the aspects of the present invention the way programming steps occur in multilevel flash memories will be examined hereafter.
The writing operation of a flash cell consists in varying the threshold voltage thereof by the amount desired, storing electrons in the floating gate region.
In order to program the cell with threshold voltage distributions having enough precision to manufacture the cell, the voltage applied on the control gate terminal can be step-variable from a minimum value up to a maximum value; the amplitude of the voltage step, in drain-terminal optimum conditions, is equal to the threshold jump to be obtained.
The use of a step-gate voltage poses a time problem to successfully accomplish the programming step; to minimize the duration of programming times it is often necessary to program a high number of cells in parallel.
In parallel multilevel programming, the most used programming algorithm is called “program & verify” and it consists in a sequence of programming pulses and controls during whose execution each programming pulse is followed by a reading step of the cells being programmed, to control if they have reached the threshold value or not.
The value of the gate voltage is increased at each pulse, keeping the drain voltage constant. Between consecutive programming pulses, the cells are controlled and if they have reached the desired state, they are removed from the set of cells to be programmed.
In order to increase the programming throughput, more words are programmed in parallel. The programming of more words requires higher currents and this implies designing charge pumps having higher-current capacities.
Moreover, the parallel programming of more words also means the parallel control thereof. The trend in multilevel memories is to perform controls being as similar as possible to readings, except for the reference position. A control intrinsic difference, with respect to reading, is linked to the state of word cells. During programming the cell state is evolving and thus each control will have different outline conditions. During a reading the cell state is fixed.
An important outline condition is linked to the bias of the source terminal.
The cell source bias inevitably occurs through a resistive path. The real source voltage depends then on the current flowing in the bias line thereof, and this current depends on the overall state of the word cells being controlled.
The effect of this source resistance will be briefly described. For simplicity the programming of two cells will only be considered, the first from state “11” to state “10”, the second from state “11” to state “00”, making reference to the schematic example of FIG. 1.
The programming starts with a sequence of programming and control pulses. During controls both cells carry the current. At a certain point the first cell reaches the state “10”, it is released and programming continues up to bring the second cell in the state “00”.
If at this point a new control of the two cells is performed, the situation seems changed. In fact, at the beginning of the algorithm, the source of the first cell was at a higher potential than the potential reached when the second cell reaches the state “00”.
Therefore, the cell “10” is more conductive, and in practice it is as if it shifted towards the distribution “11”.
A technical solution has been recently provided to remedy the phenomenon being described, which consists in modifying the programming algorithm with a mode called “Repeated Slope”. In substance, it consists of controlling again the cell state at the end of the programming and eventually in reprogramming only those cells that were shifted towards an erasing state.
This solution involves, however, a time extension because of the changes following the control.